What is TINKER?

Since 1994, the TINKER project at NC State has removed traditional of layers of abstraction to uncover new techniques for high performance microprocessors. The project has focused on breaking down the layers between the microarchitecture, the instruction set, the compiler and the operating system. The first direction of the project was the creation of an EPIC/VLIW test bed for both general-purpose and embedded applications, the study of very wide EPIC machines, and the study of variable grainsize parallel processing. This now includes a rich suite of simulators, a compiler, synthesizable HDL designs, and custom-silicon implementations of example designs. The project also addresses new techniques for solving some of the traditional problems of statically-scheduled machines. These problems include poor memory usage, the practicality of profile-driven scheduling, and lack of object-code compatibility between generations.

The core semantics of the TINKER processor testbed were initally taken from the HP Laboratories PlayDoh architecture (which in turn had a large influence on the HP/Intel IA-64 instruction set). PlayDoh (now officially called HPL-PD) is a set of VLIW semantics developed by Vinod Kathail, Mike Schlansker and B. Ramakrishna Rau of Hewlett-Packard's Compilers and Architecture Research group. The specification defines a class of instruction sets with the following properties, among others:

The TINKER set of instruction semantics, instruction encodings and microarchitectural techniques add the following to the base PlayDoh semantics:

Current research directions include dynamic compilation by merging the compiler with the operating system, ultra low power designs using microarchitecture / ISA / compiler collaborations, enhanced micro threading to hide memory latencies, and new techniques for global instruction scheduling.

Bibliography (for copies see the TINKER research publications page):

[1] T. M. Conte, B. A. Patel, K. N. Menezes and J. S. Cox, ``Hardware-based profiling: An effective technique for profile-driven optimization,'' International Journal of Parallel Programming, vol. 24, no. 2, Feb. 1996.

[2] T. M. Conte, K. N. Menezes and M. A. Hirsch, ``Accurate and practical profile-driven compilation using the profile buffer''. In Proceedings of the 29th Annual International Symposium on Microarchitecture, (Paris, France), pp.36-45, Dec. 1996.

[3] K. N. P. Menezes, ``Hardware-based profiling for program optimization,'' Ph.D. thesis, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, 1997.

[4] M. D. Jennings, "Multimedia Extensions to TINKER", Technical Report, Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911, June 1995.

[5] C. Fu, M. D. Jennings, S. Y. Larin and T. M. Conte, " Value Speculation Scheduling for High Performance Processors," in Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), (San Jose, CA), Oct. 4-7, 1998.

[6] C. Fu, M. D. Jennings, S. Y. Larin and T. M. Conte, " Software-Only Value Speculation Scheduling ," Technical Report. Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911, June, 1998.

[7] E. Ozer, S. Banerjia, T. M. Conte, "Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures," in Proceedings of the 31st Annual International Symposium on Microarchitecture, (Dallas, TX), Nov. 1998.